Military microelectronics experts at the U.S. Defense Advanced Research Projects Agency (DARPA) in Arlington, Va., are launching a leap-ahead technology program to develop advanced, ultra-low-power non-volatile logic integrated circuits that retain their data and computational states when power is removed.
The NV Logic program seeks to develop a complete library of logic elements and building blocks that perform logical functions using new computational state variables such as magnetization.
Ultimately, scientists at the DARPA Microsystems Technology Office (MTO) want this program to develop technologies to enable no less than a new computational paradigm for ultra-low-power electronics such as remote sensors, portable electronics, small unmanned aerial vehicles (UAVs), and high-performance computing.
Today's CMOS non-volatile logic devices perform computation using the movement of charge under the influence of electric fields. Instead, DARPA experts want to reduce power consumption by developing logic devices based on another computational state variable, which most likely will be magnetic moment.
This approach not only retains its computational state when the power is removed, but it also is intrinsically radiation hardened due to its use of ferromagnetic materials, DARPA officials say.
The NV Logic program seeks to demonstrates circuits that not only use magnetic moments instead of charge to perform computation, but also communicate via conventional electrical wire signals to other circuits. These NV Logic circuits should display lower power per operation while having computational density equal to or better than state-of–the-art circuits that use charge.
The NV Logic program has three technical areas of interest: the switching behavior of nanoscale magnetic materials and the interaction of several magnetic domains; fabrication and testing of the non-volatile logic circuit; and developing novel circuits and circuit design tools.
The program most likely will be no longer than 4 1/2 years, with a two-year proof of concept stage, and a 2 1/2-year to refine and demonstrate a simple circuit, and compare its performance to conventional CMOS technology.
The first stage, might demonstrate a 2-bit adder with switching speed of 10 nanoseconds, a circuit area of 25 square microns, and power consumption of 100 attojoules per operation. The second stage might demonstrate a 2-bit adder with 1-nanosecond switching speed, a circuit area of 1 square micron, and power consumption of 10 attojoules per operation.
DARPA experts say the expect to make several contract awards. Companies interested should send proposals to DARPA no later than 21 April 2010.
For questions or concerns, contact DARPA's Devanand Shenoy by e-mail at DARPA-BAA-10-42@darpa.mil, by fax at 703-696-2206, or by post at DARPA/MTO, ATTN: DARPA-BAA-10-42, 3701 North Fairfax Dr., Arlington, VA 22203-1714.
